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FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
February 2010
FSEZ1307 Primary-Side-Regulation PWM with Power MOSFET Integrated
Features
Low Standby Power: Under 30mW High-Voltage Startup Few External Components Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Green Mode: Linearly Decreasing PWM Frequency Fixed PWM Frequency at 50kHz with Frequency Hopping to Solve EMI Problem Cable Compensation in CV Mode Peak-Current-Mode Control in CV Mode Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection with Auto Restart VDD Under-Voltage Lockout (UVLO) Gate Output Maximum Voltage Clamped at 15V Fixed Over-Temperature Protection with Auto Restart Available in 7-Lead SOP Package
Description
This third-generation Primary Side Regulation (PSR) PWM controller combination power MOSFET, FSEZ1307, provides several features to enhance the performance of low-power flyback converters. The proprietary topology, TRUECURRENTTM, enables precise CC regulation and simplified circuit design for battery-charger applications. Compared to a conventional design or a linear transformer, a low-cost, smaller, and lighter charger results. To minimize standby power consumption, the proprietary green mode provides off-time modulation to linearly decrease PWM frequency under light-load conditions. Green mode assists the power supply in meeting power conservation requirements. By using the FSEZ1307, a charger can be implemented with few external components and minimized cost. A typical output CV/CC characteristic envelope is shown in Figure 1.
Applications
Battery chargers for cellular phones, cordless phones, PDA, digital cameras, power tools, etc. Replaces linear transformers and RCC SMPS
Figure 1. Typical Output V-I Characteristic
Ordering Information
Part Number
FSEZ1307MY
Operating Temperature Range
-40C to +105C
Eco Status
Green
Package
7-Lead, Small Outline Package (SOP-7)
Packing Method
Tape & Reel
For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
www.fairchildsemi.com
FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
Application Diagram
Rsn L1 Rsn2 D1 RF AC Input D2 D3 Rsn1 C1 C2 CVDD DFa CVS
2 VDD 7 HV VS 5 DRAIN 8 1
Csn2
T1 Csn DF CO1 Dsn CO2 Rd DC Output
D4
R1
R2
CS 3 GND
COMR 4
RSENSE
CCR
Figure 2. Typical Application
Internal Block Diagram
Figure 3. Functional Block Diagram
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2 www.fairchildsemi.com 2
FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
Marking Information
F: Fairchild Logo Z: Plant Code X: 1-Digit Year Code Y: 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (M=SOP) P: Y=Green Package M: Manufacture Flow Code
Figure 4. Top Mark
Pin Configuration
Figure 5. Pin Configuration
Pin Definitions
Pin #
1 2 3 4 5 7 8
Name
CS VDD GND COMR VS HV DRAIN
Description
Current Sense. This pin connects a current-sense resistor to detect the MOSFET current for peak-current-mode control in CV mode and provides the output-current regulation in CC mode. Power Supply. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external VDD capacitor of typically 10F. The threshold voltages for startup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA. Ground Cable Compensation. This pin connects a 1F capacitor between the COMR and GND pins for compensation voltage drop due to output cable loss in CV mode. Voltage Sense. This pin detects the output voltage information and discharge time based on voltage of auxiliary winding. High Voltage. This pin connects to a bulk capacitor for high-voltage startup. Driver Output. Power MOSFET drain. This pin is the high-voltage power MOSFET drain.
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VHV VVDD VVS VCS VCOMV VCOMI VDS ID IDM EAS IAR PD JA JC TJ TSTG TL ESD HV Pin Input Voltage DC Supply Voltage
(1,2)
Parameter
Min.
Max.
500 30
Units
V V V V V V V A A A mJ A mW C/W C/W C C C V
VS Pin Input Voltage CS Pin Input Voltage Voltage Error Amplifier Output Voltage Current Error Amplifier Output Voltage Drain-Source Voltage Continuous Drain Current Pulsed Drain Current Single Pulse Avalanche Energy Avalanche Current Power Dissipation (TA50C) Thermal Resistance (Junction to Air) Thermal Resistance (Junction to Case) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Electrostatic Discharge Capability Human Body Model (Except HV Pin), JEDEC-JESD22_A114 Charged Device Model (Except HV Pin), JEDEC-JESD22_C101 TA=25C TA=100C
-0.3 -0.3 -0.3 -0.3
7.0 7.0 7.0 7.0 700 0.5 0.35 3.5 35 1 660 150 39
-40 -55
+150 +150 +260 2500 1250
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to the GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Min.
-40
Max.
+105
Units
C
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
Electrical Characteristics
Unless otherwise specified, VDD=15V and TA=25.
Symbol
VDD Section VOP VDD-ON VDD-OFF IDD-OP IDD-GREEN VDD-OVP VDD-OVP-HYS tD-VDDOVP VHV-MIN IHV IHV-LC
Parameter
Continuously Operating Voltage Turn-On Threshold Voltage Turn-Off Threshold Voltage Operating Current Green-Mode Operating Supply Current VDD Over-Voltage-Protection Level (OVP) Hysteresis Voltage for VDD OVP VDD Over-Voltage-Protection Debounce Time Minimum Startup Voltage on HV Pin Supply Current Drawn from HV Pin Leakage Current after Startup
Conditions
Min.
Typ.
Max. Units
23 V V V mA mA V 2.5 300 50 V s V mA A
15 4.5
16 5.0 2.5 0.95 24
17 5.5 5.0 1.20
1.5 50
2.0 200
HV Startup Current Source Section VDC=100V HV=500V, VDD= VDDOFF+1V 47 1.5 1.5 0.96 3.0 3.00
Oscillator Section fOSC fOSC-N-MIN fOSC-CM-MIN fDV fDT Frequency Center Frequency Frequency Hopping Range 50 2.0 370 13 VDD=10~25V, TA=-40C to 105C 10 RVS=20k 1.4 90 700 850 0.8 2.475 fOSC-2kHz fOSC=1kHz 2.475 2.500 2.5 0.4 2.500 0.75 2.525 2.525 200 1050 1 2 15 53 2.5 kHz Hz kHz % %
Minimum Frequency at No-Load Minimum Frequency at CCM Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation
Voltage-Sense Section Itc VBIAS-COMV tPD tMIN-N VTH VVR VN VG VIR VCOMR IC Bias Current Adaptive Bias Voltage Dominated by VCOMV Propagation Delay to GATE Output Minimum On Time at No-Load Threshold Voltage for Current Limit Reference Voltage Green-Mode Starting Voltage on EA_V Green-Mode Ending Voltage on EA_V Reference Voltage COMR Pin for Cable Compensation A V ns ns V V V V V V
Current-Sense Section
Voltage-Error-Amplifier Section
Current-Error-Amplifier Section Cable Compensation Section
Continued on the following page...
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
Electrical Characteristics (Continued)
Unless otherwise specified, VDD=15V and TA=25.
Symbol
Internal MOSFET Section DCYMAX BVDSS
(3)
Parameter
Maximum Duty Cycle Drain-Source Breakdown Voltage
Conditions
Min.
70
Typ.
75
Max.
80
Units
% V
ID=250A, VGS=0V ID=250A, Referenced to TA=25C ID=0.5A, VGS=10V
700
BVDSS/TJ
Breakdown Voltage Temperature Coefficient
0.53
V/C
RDS(ON) IS
Static Drain-Source On-Resistance Maximum Continuous Drain-Source Diode Forward Current
17
20 0.5
A A A ns ns pF pF C
IDSS
Drain-Source Leakage Current
VDS=700V, TA=25C VDS=560V, TA=100C VDS=350V, ID=1A, (4) RG=25 VGS=0V, VDS=25V, fS=1MHz 10 20 125 15
(5)
10 100 30 50 150 18
tD-ON tD-OFF CISS COSS TOTP
Turn-On Delay Time Turn-Off Delay Time Input Capacitance Output Capacitance Threshold Temperature for OTP
Over-Temperature-Protection Section 140 Notes: 3. These parameters, although guaranteed, are not 100% tested in production. 4. Pulse test: pulsewidth 300s, duty cycle 2%. 5. When the Over-temperature protection is activated, the power system enter latch mode and output is disabled.
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
Typical Performance Characteristics
17 5.5
16.6
5.3
16.2
VDD_OFF (V)
-40 -30 -15 0 25 50 75 85 100 125
VDD_ON (V)
5.1
15.8
4.9
15.4
4.7
15
4.5 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 6.
Turn-On Threshold Voltage (VDD-ON) vs. Temperature
Figure 7.
Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature
4 3.5
54 52
IDD_OP (mA)
2.5 2 1.5 1 -40 -30 -15 0 25 50 75 85 100 125
Fosc (KHz)
3
50 48 46 44 42 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 8.
Operating Current (IDD-OP) vs. Temperature
Figure 9.
Center Frequency (fOSC) vs. Temperature
2.53 2.52 2.51
1.1 1.05
IDD_Green (mA)
-40 -30 -15 0 25 50 75 85 100 125
1 0.95 0.9 0.85 0.8 -40 -30 -15 0 25 50 75 85 100 125
VVR (V)
2.5 2.49 2.48 2.47
Temperature (C)
Temperature (C)
Figure 10. Reference Voltage (VVR) vs. Temperature
Figure 11. Green-Mode Operating Supply Current (IDD-GREEN) vs. Temperature
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
Typical Performance Characteristics
400 15
360
Fosc_CM_MIN (KHz)
-40 -30 -15 0 25 50 75 85 100 125
380
14
Fosc_Green (Hz)
13
340
12
320
11
300
10 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 12. Minimum Frequency at No Load (fOSC-N-MIN) vs. Temperature
Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN) vs. Temperature
3 2.5 2 1.5 1 0.5 0 -40 -30 -15 0 25 50 75 85 100 125
1000
950
TMIN_N (ns)
IHV (mA)
900
850
800
750 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 14. Supply Current Drawn from HV Pin (IHV) vs. Temperature
Figure 15. Minimum On Time at No Load (tMIN-N) vs. Temperature
2.6
0.44
2.55
0.43
Vn (V)
2.45
Vg (V)
-40 -30 -15 0 25 50 75 85 100 125
2.5
0.42
0.41
2.4
0.4
2.35
0.39 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 16. Green-Mode Starting Voltage on EA_V (VN) vs. Temperature
Figure 17. Green-Mode Ending Voltage on EA_V (VG) vs. Temperature
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
Typical Performance Characteristics
10.5 10 9.5 2
VBIAS_COMV (V)
-40 -30 -15 0 25 50 75 85 100 125
1.7
ITC (uA)
1.4
9 8.5 8 7.5
1.1
0.8
0.5 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 18. IC Bias Current (Itc) vs. Temperature
Figure 19. Adaptive Bias Voltage Dominated by VCOMV (VBIAS-COMV) vs. Temperature
0.87 0.85 0.83
14 12
IHV_LC (uA)
-40 -30 -15 0 25 50 75 85 100 125
10 8 6 4 2 -40 -30 -15 0 25 50 75 85 100 125
VTH (V)
0.81 0.79 0.77 0.75
Temperature (C)
Temperature (C)
Figure 20. Threshold Voltage for Current Limit (VTH) vs. Temperature
Figure 21. Leakage Current after Startup (IHV-LC) vs. Temperature
0.78 0.77
80
78
DCYMax (%)
-40 -30 -15 0 25 50 75 85 100 125
VCOMR (V)
0.76 0.75 0.74 0.73 0.72
76
74
72
70 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 22. Variation Test Voltage on COMR Pin for Cable Compensation (VCOMR) vs. Temperature
Figure 23. Maximum Duty Cycle (DCYMAX) vs. Temperature
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with Power MOSFET Integrated
Functional Description
Figure 24 shows the basic circuit diagram of primaryside regulated flyback converter, with typical waveforms shown in Figure 25. Generally, discontinuous conduction mode (DCM) operation is preferred for primary-side regulation because it allows better output regulation. The operation principles of DCM flyback converter are as follows: During the MOSFET on time (tON), input voltage (VDL) is applied across the primary-side inductor (Lm). Then MOSFET current (Ids) increases linearly from zero to the peak value (Ipk). During this time, the energy is drawn from the input and stored in the inductor. When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to be turned on. While the diode is conducting, the output voltage (Vo), together with diode forward-voltage drop (VF), is 2 applied across the secondary-side inductor (LmxNs / 2 Np ) and the diode current (ID) decreases linearly from the peak value (IpkxNp/Ns) to zero. At the end of inductor current discharge time (tDIS), all the energy stored in the inductor has been delivered to the output. When the diode current reaches zero, the transformer auxiliary winding voltage (Vw) begins to oscillate by the resonance between the primary-side inductor (Lm) and the effective capacitor loaded across the MOSFET. During the inductor current discharge time, the sum of output voltage and diode forward-voltage drop is reflected to the auxiliary winding side as (Vo+VF) x Na/Ns. Since the diode forward-voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time where the diode current diminishes to zero. Thus, by sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. The internal error amplifier for output voltage regulation (EA_V) compares the sampled voltage with internal precise reference to generate error voltage (VCOMV), which determines the duty cycle of the MOSFET in CV mode. Meanwhile, the output current can be estimated using the peak drain current and inductor current discharge time because output current is same as the average of the diode current in steady state. The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the inductor discharge time (tDIS) and switching period (ts). This output information is compared with internal precise reference to generate the error voltage (VCOMI), which determines the duty cycle of the MOSFET in CC mode. With Fairchild's innovative TRUECURRENTTM technique, constant current (CC) output can be precisely controlled. Among the two error voltages, VCOMV and VCOMI, the smaller one determines the duty cycle. Therefore, during constant voltage regulation mode, VCOMV determines the duty cycle while VCOMI is saturated to HIGH. During constant current regulation mode, VCOMI determines the duty cycle while VCOMV is saturated to HIGH.
Np:Ns D + V DL Lm
ID
IO + VO L O A D
+ VF -
VAC
Ids
EA_I V COMI PWM Control V COMV EA_V IO Estimator Ref t DIS Detector VO Estimator Ref
CS RCS
VS VDD RS1 RS2 NA + Vw -
Primary-Side Regulation Controller
Figure 24. Simplified PSR Flyback Converter Circuit
I pk
I pk
NP NS
I D.avg = I o
VF
NA NS
VO
NA NS
Figure 25. Key Waveforms of DCM Flyback Converter
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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Cable Voltage Drop Compensation
In cellular phone charger applications, the battery is located at the end of cable, which typically causes several percentage points of voltage drop on the battery voltage. FSEZ1307 has a built-in cable voltage drop compensation that provides a constant output voltage at the end of the cable over the entire load range in CV mode. As load increases, the voltage drop across the cable is compensated by increasing the reference voltage of the voltage regulation error amplifier.
Operating Current
The FSEZ1307 operating current is as small as 2.5mA, which results in higher efficiency and reduces the VDD hold-up capacitance requirement. Once FSEZ1307 enters "deep" green mode, the operating current is reduced to 0.95mA, assisting the power supply in meeting power conservation requirements.
Green-Mode Operation
The FSEZ1307 uses voltage regulation error amplifier output (VCOMV) as an indicator of the output load and modulates the PWM frequency, as shown in Figure 26. The switching frequency decreases as the load decreases. In heavy load conditions, the switching frequency is fixed at 50kHz. Once VCOMV decreases below 2.5V, the PWM frequency linearly decreases from 50kHz. When FSEZ1307 enters deep green mode, the PWM frequency is reduced to a minimum frequency of 370Hz, gaining power saving to meet international power conservation requirements. Figure 27. Frequency Hopping
High-Voltage Startup
Figure 28 shows the HV-startup circuit for FSEZ1307 applications. The HV pin is connected to the line input or bulk capacitor through a resistor, RSTART (100k recommended). During startup, the internal startup circuit is enabled. Meanwhile, line input supplies the current, ISTARTUP, to charge the hold-up capacitor, CDD, through RSTART. When the VDD voltage reaches VDD-ON, the internal startup circuit is disabled, blocking ISTARTUP from flowing into the HV pin. Once the IC turns on, CDD is the only energy source to supply the IC consumption current before the PWM starts to switch. Therefore, CDD must be large enough to prevent VDD from dropping down to VDD-OFF before the power can be delivered from the auxiliary winding.
Figure 26. Switching Frequency in Green Mode
Frequency Hopping
EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. FSEZ1307 has an internal frequency hopping circuit that changes the switching frequency between 47kHz and 53kHz over the period shown in Figure 27. Figure 28. HV Startup Circuit
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at 16V and 5V, respectively. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable the FSEZ1307. The hold-up capacitor continues to supply VDD until power can be delivered from the auxiliary winding of the main transformer. VDD is not allowed to drop below 5V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor properly supplies VDD during startup.
Over-Temperature Protection (OTP) The built-in temperature-sensing circuit shuts down PWM output if the junction temperature exceeds 140C. Pulse-by-Pulse Current Limit When the sensing voltage across the current-sense resistor exceeds the internal threshold of 0.8V, the MOSFET is turned off for the remainder of switching cycle. In normal operation, the pulse-by-pulse current limit is not triggered since the peak current is limited by the control loop. Leading-Edge Blanking (LEB) Each time the power MOSFET switches on, a turn-on spike occurs at the sense resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. As a result, conventional RC filtering can be omitted.
Protections
The FSEZ1307 has several self-protection functions, such as Over-Voltage Protection (OVP), OverTemperature Protection (OTP), and pulse-by-pulse current limit. All the protections are implemented as auto-restart mode. Once the abnormal condition occurs, the switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD turn-off voltage of 5V, the internal startup circuit is enabled again and the supply current drawn from the HV pin charges the hold-up capacitor. When VDD reaches the turn-on voltage of 16V, normal operation resumes. In this manner, the auto-restart alternately enables and disables the switching of the MOSFET until the abnormal condition is eliminated (see Figure 29).
Gate Output
The FSEZ1307 output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 15V Zener diode to protect the power MOSFET transistors against undesired over-voltage gate signals.
Built-In Slope Compensation
The sensed voltage across the current-sense resistor is used for current mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillations due to peak-current mode control. The FSEZ1307 has a synchronized, positive-slope ramp built-in at each switching cycle.
Noise Immunity
Noise from the current sense or the control signal can cause significant pulsewidth jitter, particularly in continuous-conduction mode. While slope compensation helps alleviate these problems, further precautions should still be taken. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FSEZ1307, and increasing the power MOS gate resistance are advised. Figure 29. Auto-Restart Operation
VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents damage from overvoltage conditions. If the VDD voltage exceeds 24V at open-loop feedback condition, OVP is triggered and the PWM switching is disabled. The OVP has a debounce time (typically 200s) to prevent false triggering due to switching noises.
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 --Primary-Side-Regulation PWM with POWER MOSFET Integrated
Typical Application Circuit (Primary-Side Regulated Flyback Charger)
Application Cell Phone Charger Fairchild Device FSEZ1307 Input Voltage Range 90~265VAC Output 5V/0.7A (3.5W) Output DC cable AWG26, 1.8 Meter
Features
High efficiency (>65.5% at full load) meeting EPS 2.0 regulation with enough margin Low standby (Pin<30mW at no-load condition)
Figure 30. Measured Efficiency
Figure 31.
Standby Power
Figure 32. Schematic of Typical Application Circuit
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with POWER MOSFET Integrated
Typical Application Circuit (Continued)
Transformer Specification
Core: EE16 Bobbin: EE16
Figure 33. Transformer Specification Notes: 6. When W4R's winding is reversed winding, it must wind one layer. 7. When W2 is winding, it must wind three layers and put one layer of tape after winding the first layer.
NO
W1 W2 W3 W4
TERMINAL S
4 3 1 7 9
F
5 1
WIRE
2UEW 0.23*2 2UEW 0.17*1 COPPER SHIELD TEX-E 0.55*1 CORE ROUNDING TAPE
ts
15 41 39 37 1.2 9
INSULATION ts
2 1 0 2 3 3 3
BARRIER TAPE Primary Seconds
Pin
Primary-Side Inductance Primary-Side Effective Leakage 13 13
Specification
2.25mH 7% 80H 5%
Remark
100kHz, 1V Short One of the Secondary Windings
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with POWER MOSFET Integrated
Physical Dimensions
5.00 4.80 3.81
8 7 5
A
0.65
B
6.20 5.80
1.75 4.00 3.80 5.60
PIN ONE INDICATOR
1
4
1.27
0.25
M
(0.33)
CBA
1.27
LAND PATTERN RECOMMENDATION SEE DETAIL A
0.25 0.10 1.75 MAX 0.51 0.33 R0.10 R0.10 0.50 x 45 0.25
C 0.10 C
0.25 0.19
OPTION A - BEVEL EDGE
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
8 0
0.90 0.406
DETAIL A
SCALE: 2:1
NOTES: A) THIS PACKAGE CONFORMS TO JEDEC MS-012 VARIATION AA EXCEPT FOR MISSING PIN 6. B) ALL DIMENSIONS ARE IN MILLIMETERS. SEATING PLANE C) DIMENSIONS DO NOT INCLUDE MOLD (1.04) FLASH OR BURRS. D) DRAWING FILENAME: M07BREV2
Figure 34. 7-Lead, Small Outline Package (SOP-7)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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FSEZ1307 -- Primary-Side-Regulation PWM with POWER MOSFET Integrated
(c) 2010 Fairchild Semiconductor Corporation FSEZ1307 * Rev. 1.0.2
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